ECC Design Center

The image above is an actual image from the James Webb Space Telescope (JWST).  To the best of my knowledge, all the data collected by the JWST is being encoded and decoded by error-correcting circuits I licensed to NASA which correct random errors and errors caused by chip failures.

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I started a Minnesota corporation in 1990 named ECC Technologies, Inc. (ECC Tek) to license software and hardware designs for encoding and decoding Reed-Solomon (RS) and binary BCH (bBCH) error-correcting codes (ECC).  Software was written in C and hardware was described in synthesizable Verilog.  ECC Tek was dissolved in 2018, and all of its intellectual property was assigned to me.

Unlike coding theorists and pure mathematicians, I am a practical digital design engineer, and my focus has been on developing practical, down-to-earth designs described in synthesizable Verilog and in developing ECC tools written in C to simulate and test the designs and also to help in developing new designs.

The following NASA missions are using error correction designs I developed:

The following is a list of companies that have licensed error correction encoder and decoder designs or other IP I developed:

All parties who have licensed designs from me are happy with the results, and the performance of my designs usually exceeds their performance requirements.

I have been involved with error-correcting codes for more than 50 years - since 1973 - and have developed and licensed C and synthesizable Verilog code for many encoder and decoder designs and ECC design tools.

If you are interested in purchasing all of the IP I own, please contact me.

The IP I own includes the following items:

Since some of the existing designs were developed a number of years ago before the ECC design tools were developed, I would recommend using the most recent IP to develop any type of RS or binary BCH design you may need although the existing designs can be synthesized immediately with no development effort.